The Opteron is AMD's x86 server processor line, and was the first processor to implement the AMD64 instruction set architecture (known generically as x86-64). It was released on April 22, 2003 with the SledgeHammer core (K8) and was intended to compete in the server market, particularly in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture (codenamed Barcelona) were announced on September 10, 2007 featuring a new quad-core configuration.

Technical description

Two key capabilities

Opteron combines two important capabilities in a single processor die:

1. native execution of legacy x86 32-bit applications without speed penalties
2. native execution of x86-64 64-bit applications

The first capability is notable because at the time of Opteron's introduction, the only other 64-bit processor architecture marketed with 32-bit x86 compatibility (Intel's Itanium) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as all major RISC makers (Sun SPARC, DEC Alpha, HP PA-RISC, IBM POWER, SGI MIPS, etc.) have had 64-bit implementations for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade-path to 64-bit computing.

The Opteron processor possesses an integrated DDR SDRAM / DDR2 SDRAM (Socket AM2/F) memory controller. This both reduces the latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip.

Multi-processor features

In multi-processor systems (more than one Opteron on a single motherboard), the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing as instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel XeonFact: date=February 2007. This is primarily because adding an additional Opteron processor increases bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a switched fabric, rather than a shared bus. In particular, the Opteron's integrated memory controller allows the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a Xeon system, contention for the shared bus causes computing efficiency to drop.